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| www..com AMIS-42770 Dual High Speed CAN Transceiver General Description Controller Area Network (CAN) is a serial communication protocol, which supports distributed real-time control and multiplexing with high safety level. Typical applications of CAN-based networks can be found in automotive and industrial environments. The AMIS-42770 Dual-CAN transceiver is the interface between up to two physical bus lines and the protocol controller and will be used for serial data interchange between different electronic units at more than one bus line. It can be used for both 12 V and 24 V systems. The circuit consists of following blocks: * Two differential line transmitters * Two differential line receivers * Interface to the CAN protocol handler * Interface to expand the number of CAN busses * Logic block including repeater function and the feedback suppression * Thermal shutdown circuit (TSD) Due to the wide common-mode voltage range of the receiver inputs, the AMIS-42770 is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. Key Features http://onsemi.com SOIC 20 IC SUFFIX CASE 751AQ ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. * Fully Compatible with the ISO 11898-2 Standard * Certified "Authentication on CAN Transceiver Conformance (d1.1)" * Wide Range of Bus Communication Speed (up to 1 Mbit/s in * Allows Low Transmit Data Rate in Networks Exceeding 1 km * Ideally Suited for 12 V and 24 V Industrial and Automotive * Low EME: Common-mode-choke is No Longer Required * Differential Receiver with Wide Common-mode Range (35 V) for * No Disturbance of the Bus Lines with an Un-powered Node * Prolonged Dominant Time-out Function Allowing Communication * * * * Speeds Down to 1 kbit/s Thermal Protection Bus Pins Protected against Transients Short Circuit Proof to Supply Voltage and Ground This is a Pb-Free Device* High EMS Applications Function of the Bus Topology) *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2009 January, 2009 - Rev. 3 1 Publication Order Number: AMIS-42770/D AMIS-42770 www..com ORDERING INFORMATION Part Number AMIS42770ICAW1G AMIS42770ICAW1RG Package SOIC-20 300 GREEN SOIC-20 300 GREEN Shipping Configuration Tube/Tray Tape & Reel Temperature Range -40C to 125C -40C to 125C Table 1. TECHNICAL CHARACTERISTICS Symbol VCANHx VCANLx Vo(dif)(bus_dom) CM-range VCM-peak VCM-step Parameter DC voltage at pin CANH1/2 DC voltage at pin CANL1/2 Differential bus output voltage in dominant state Input common-mode range for comparator Common-Mode peak Common-Mode step Conditions 0 < VCC < 5.25 V; no time limit 0 < VCC < 5.25 V; no time limit 42.5 W < RLT < 60 W Guaranteed differential receiver threshold and leakage current See Figures 10 and 11 (Note 1) See Figures 10 and 11 (Note 1) Min. -45 -45 1.5 -35 -1000 -250 Max. +45 +45 3 +35 +1000 +250 Unit V V V V mV mV 1. The parameters VCM-peak and VCM-step guarantee low EME. VCC 12 Thermal shutdown POR 2 x timer clock CANH1 CANL1 13 14 AMIS-42770 Feedback Suppression Feedback Suppression Driver control Timer Driver control Timer 19 18 CANH2 CANL2 Logic Unit Ri(cm) VCC/2 - + Ri(cm) COMP VCC VCC COMP VCC Ri(cm) VCC/2 + - Ri(cm) VCC 8 VREF 10 ENB1 3 Text 4 7 9 Rint 2 ENB2 5 6 15 16 17 GND Tx0 Rx0 Figure 1. Block Diagram http://onsemi.com 2 AMIS-42770 www..com TYPICAL APPLICATION Application Description AMIS-42770 is especially designed to provide the link between a CAN controller (protocol IC) and two physical busses. It is able to operate in three different modes: * Dual CAN * A CAN-bus extender * A CAN-bus repeater Application Schematics VBAT 5 V-reg CD 100 nF VCC EN1 EN2 Rx0 Tx0 Text Rint 10 2 7 4 3 9 5 6 15 16 17 18 GND CANL2 14 AMIS-42770 19 12 Vref 8 13 CANH1 CANL1 CANH2 RLT 60 W RLT 60 W CAN BUS 1 CAN BUS 2 Figure 2. Application Diagram CAN-bus Repeater VBAT 5 V-reg CD 100 nF VCC EN1 EN2 Rx0 mC CAN controller Tx0 Text Rint VCC 10 2 7 4 3 9 5 6 15 16 17 18 GND CANL2 14 AMIS-42770 19 12 CD 100 nF Vref 8 13 CANH1 CANL1 CANH2 RLT 60 W RLT 60 W CAN BUS 1 CAN BUS 2 GND Figure 3. Application Diagram Dual-CAN http://onsemi.com 3 AMIS-42770 www..com VBAT 5 V-reg CD 100 nF VCC EN1 EN2 Rx0 mC CAN controller Tx0 Text Rint GND VCC 10 2 7 4 3 9 5 6 15 16 17 18 GND CANL2 AMIS-42770 14 19 12 CD 100 nF Vref 8 13 CANH1 CANL1 CANH2 RLT 60 W RLT 60 W CAN BUS 1 CAN BUS 2 isolated +5 Dual OptoCoupler VCC EN1 EN2 Rx0 Tx0 Text Rint 10 2 7 4 3 9 5 6 15 16 17 18 GND CANL2 14 AMIS-42770 19 12 CAN BUS 3 CAN BUS 4 CD 100 nF Vref 8 13 CANH1 CANL1 CANH2 RLT 60 W RLT 60 W Figure 4. Application Diagram CAN-bus Extender NC EN2 Text Tx0 GND GND Rx0 Vref1 Rint EN1 1 2 3 4 5 6 7 8 9 10 AMIS-42770 4 20 NC 19 CANH2 18 CANL2 17 GND 16 GND 15 GND 14 CANL1 13 CANH1 12 VCC 11 NC Figure 5. Pin Out (top view) http://onsemi.com AMIS-42770 www..com Table 2. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name NC ENB2 Text Tx0 GND GND Rx0 VREF1 Rint ENB1 NC VCC CANH1 CANL1 GND GND GND CANL2 CANH2 NC Not connected Enable input, bus system 2; internal pull-up Multi-system transmitter Input; internal pull-up Transmitter input; internal pull-up Ground connection (Note 2) Ground connection (Note 2) Receiver output Reference voltage Multi-system receiver output Enable input, bus system 1; internal pull-up Not connected Positive supply voltage CANH transceiver I/O bus system 1 CANL transceiver I/O bus system 1 Ground connection (Note 2) Ground connection (Note 2) Ground connection (Note 2) CANL transceiver I/O bus system 2 CANH transceiver I/O bus system 2 Not connected Description 2. In order to ensure the chip performance, all these pins need to be connected to GND on the PCB. FUNCTIONAL DESCRIPTION Overall Functional Description AMIS-42770 is specially designed to provide the link between the protocol IC (CAN controller) and two physical bus lines. Data interchange between those two bus lines is realized via the logic unit inside the chip. To provide an independent switch-off of the transceiver units for both bus systems by a third device (e.g. the C), enable-inputs for the corresponding driving and receiving sections are provided. As long as both lines are enabled, they appear as one logical bus to all nodes connected to either of them. The bus lines can have two logical states, dominant or recessive. A bus is in the recessive state when the driving sections of all transceivers connected to the bus are passive. The differential voltage between the two wires is approximately zero. If at least one driver is active, the bus changes into the dominant state. This state is represented by a differential voltage greater than a minimum threshold and therefore by a current flow through the terminating resistors of the bus line. The recessive state is overwritten by the dominant state. In case a fault (like short circuit) is present on one of the bus lines, it remains limited to that bus line where it occurs. Data interchange from the protocol IC to the other bus system and on this bus system itself can be continued. AMIS-42770 can be also used for only one bus system. If the connections for the second bus system are simply left open it serves as a single transceiver for an electronic unit. For correct operation, it is necessary to terminate the open bus by the proper termination resistor. Logic Unit and CAN Controller Interface The logic unit inside AMIS-42770 provides data transfer from/to the digital interface to/from the two busses and from one bus to the other bus. The detailed function of the logic unit is described in Table 3. All digital input pins, including ENBx, have an internal pull-up resistor to ensure a recessive state when the input is not connected or is accidentally interrupted. A dominant state on the bus line is represented by a low-level at the digital interface; a recessive state is represented by a high-level. Dominant state received on any bus (if enabled) causes a dominant state on both busses, pin Rint and pin Rx0. Dominant signal on any of the input pins Tx0 and Text causes transmission of dominant on both bus lines (if enabled). Digital inputs Tx0 and Text are used for connecting the internal logic's of several IC's to obtain versions with more than two bus outputs (see Figure 4). They have also a direct logical link to pins Rx0 and Rint independently on the EN1x pins - dominant on Tx0 is directly transferred to both Rx0 and Rint pins, dominant on Text is only transferred to Rx0. http://onsemi.com 5 AMIS-42770 www..com Transmitters The transceiver includes two transmitters, one for each bus line, and a driver control circuit. Each transmitter is implemented as a push and a pull driver. The drivers will be active if the transmission of a dominant bit is required. During the transmission of a recessive bit all drivers are passive. The transmitters have a built-in current limiting circuit that protects the driver stages from damage caused by accidental short circuit to either positive supply voltage or to ground. Additionally a thermal protection circuit is integrated. The driver control circuit ensures that the drivers are switched on and off with a controlled slope to limit EME. The driver control circuit will control itself by the thermal protection circuit, the timer circuit and the logic unit. The enable signal ENBx allows the transmitter to be switched off by a third device (e.g. the C). In the disabled state (ENBx = high) the corresponding transmitter behaves as in the recessive state. Table 3. FUNCTION OF THE LOGIC UNIT (bold letters describe input signals) EN1B 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 EN2B 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 TX0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 TEXT 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 Bus 1 State dominant dominant dominant recessive dominant (Note 3) dominant dominant dominant dominant recessive dominant (Note 3) recessive recessive recessive recessive recessive dominant (Note 3) recessive recessive recessive recessive recessive dominant (Note 3) recessive Bus 2 State dominant dominant dominant recessive dominant dominant (Note 3) recessive recessive recessive recessive recessive dominant (Note 3) dominant dominant dominant recessive recessive dominant (Note 3) recessive recessive recessive recessive recessive dominant (Note 3) RX0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 RINT 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 3. Dominant detected by the corresponding receiver. Receivers Two bus receiving sections sense the states of the bus lines. Each receiver section consists of an input filter and a fast and accurate comparator. The aim of the input filter is to improve the immunity against high-frequency disturbances and also to convert the voltage at the bus lines CANHx and CANLx, which can vary from -12 V to +12 V, to voltages in the range 0 to 5 V, which can be applied to the comparators. The output signal of the comparators is gated by the ENBx signal. In the disabled state (ENBX = high), the output signal of the comparator will be replaced by a permanently recessive state and does not depend on the bus voltage. In the enabled state the receiver signal sent to the logic unit is identical to the comparator output signal. Time-out Counter To avoid that the transceiver drives a permanent dominant state on either of the bus lines (blocking all communication), time-out function is implemented. Signals on pins Tx0 and Text as well as both bus receivers are connected to the logic unit through independent timers. If the input of the timer stays dominant for longer than 25 ms (see parameter tdom), it is replaced by a recessive signal on the timer output. http://onsemi.com 6 AMIS-42770 www..com Feedback Suppression The logic unit described in Table 3 constantly ensures that dominant symbols on one bus line are transmitted to the other bus line without imposing any priority on either of the lines. This feature would lead to an "interlock" state with permanent dominant signal transmitted to both bus lines, if no extra measure is taken. Therefore feedback suppression is included inside the logic unit of the transceiver. This block masks-out reception on that bus line, on which a dominant is actively transmitted. The reception becomes active again only with certain delay after the dominant transmission on this line is finished. Power-on-Reset (POR) exceeds thermal shutdown level. Because the transmitters dissipate most of the total power, the transmitters will be switched off only to reduce power dissipation and IC temperature. All other IC functions continue to operate. Fault Behavior A fault like a short circuit is limited to that bus line where it occurs; hence data interchange from the protocol IC to the other bus system is not affected. When the voltage at the bus lines is going out of the normal operating range (-12 V to +12 V), the receiver is not allowed to erroneously detect a dominant state. Short Circuits While Vcc voltage is below the POR level, the POR circuit makes sure that: * The counters are kept in the reset mode and stable state without current consumption * Inputs are disabled (don't care) * Outputs are high impedant; only Rx0 = high-level * Analog blocks are in power down * Oscillator not running and in power down * CANHx and CANLx are recessive * VREF output high impedant for POR not released Over Temperature Detection A current-limiting circuit protects the transmitter output stage from damage caused by an accidental short-circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. The pins CANHx and CANLx are protected from automotive electrical transients (according to "ISO 7637"). ELECTRICAL CHARACTERISTICS Definitions A thermal protection circuit is integrated to prevent the transceiver from damage if the junction temperature Table 4. ABSOLUTE MAXIMUM RATINGS Symbol VCC VCANHx VCANLx VdigIO VREF Vtran(CANHx) Vtran(CANLx) Vesd(CANLx/CANHx) Vesd Latch-up Tstg Tamb Tjunc Supply voltage DC voltage at pin CANH1/2 DC voltage at pin CANL1/2 DC voltage at digital IO pins (EN1B, EN2B, Rint, Rx0, Text, Tx0) DC voltage at pin VREF Transient voltage at pin CANH1/2 Transient voltage at pin CANL1/2 ESD voltage at CANH1/2 and CANL1/2 pins ESD voltage at all other pins Static latch-up at all pins Storage temperature Ambient temperature Maximum junction temperature Parameter All voltages are referenced to GND. Positive currents flow into the IC. Sinking current means that the current is flowing into the pin. Sourcing current means that the current is flowing out of the pin. Conditions Min. -0.3 Max. +7 +45 +45 VCC + 0.3 VCC + 0.3 +150 +150 +4 +500 +2 +250 100 Unit V V V V V V V kV V kV V mA C C C 0 < VCC < 5.25 V; no time limit 0 < VCC < 5.25 V; no time limit -45 -45 -0.3 -0.3 (Note 4) (Note 4) (Note 5) (Note 7) (Note 5) (Note 7) (Note 6) -150 -150 -4 -500 -2 -250 -55 -40 -40 +155 +125 +150 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. Applied transient waveforms in accordance with "ISO 7637 part 3", test pulses 1, 2, 3a, and 3b (see Figure 6) 5. Standardized human body model (HBM) ESD pulses in accordance to MIL883 method 3015. Supply pin 8 is 2 kV. 6. Static latch-up immunity: static latch-up protection level when tested according to EIA/JESD78. 7. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993. http://onsemi.com 7 AMIS-42770 www..com Table 5. THERMAL CHARACTERISTICS Symbol Rth(vj-a) Rth(vj-s) Parameter Thermal resistance from junction to ambient in SO20 package Thermal resistance from junction to substrate of bare die Conditions In free air In free air Value 85 45 Unit K/W K/W DC CHARACTERISTICS Table 6. DC AND TIMING CHARACTERISTICS (VCC = 4.75 to 5.25 V; Tjunc = -40 to +150C; RLT = 60 W unless specified otherwise.) Symbol SUPPLY (pin VCC) ICC Supply current, no loads on digital outputs, both busses enabled Power-on-reset level on VCC High-level input voltage Low-level input voltage High-level input current Low-level input current Input capacitance VIN = VCC VIN = 0 V Not tested Dominant transmitted Recessive transmitted 2.2 45 137.5 19.5 4.7 mA Parameter Conditions Min. Typ. Max. Unit PORL_VCC V DIGITAL INPUTS (Tx0, Text, EN1B, EN2B) VIH VIL IIH IIL Ci Ioh Iol VREF VREF_CM 0.7 x VCC -0.3 -5 -75 - - - 0 -200 5 VCC 0.3 x VCC +5 -350 10 V V mA mA pF DIGITAL OUTPUTS (pin Rx0, Rint) High-level output current Low-level output current Vo = 0.7 x VCC Vo = 0.3 x VCC -50 mA < IVREF < +50 mA -35 V BUS LINES (pins CANH1/2 and CANL1/2) Vo(reces)(CANHx) Vo(reces)(CANLx) Io(reces) (CANHx) Io(reces) (CANLx) Vo(dom) (CANHx) Vo(dom) (CANLx) Vo(dif) (bus) Recessive bus voltage at pin CANH1/2 Recessive bus voltage at pin CANL1/2 Recessive output current at pin CANH1/2 Recessive output current at pin CANL1/2 Dominant output voltage at pin CANH1/2 Dominant output voltage at pin CANL1/2 Differential bus output voltage (VCANHx - VCANLx) VTx0 = VCC; no load VTx0 = VCC; no load -35 V < VCANHx < +35 V; 0 V < VCC < 5.25 V -35 V < VCANLx < +35 V; 0 V < VCC < 5.25 V VTx0 = 0 V VTx0 = 0 V VTx0 = 0 V; dominant; 42.5 W < RLT < 60 W VTxD = VCC; recessive; no load Io(sc) (CANHx) Io(sc) (CANLx) Short circuit output current at pin CANH1/2 Short circuit output current at pin CANL1/2 VCANHx = 0 V;VTx0 = 0 V VCANLx = 36 V; VTx0 = 0 V 2.0 2.0 -2.5 -2.5 3.0 0. 5 1.5 -120 -45 45 2.5 2.5 - - 3.6 1.4 2.25 0 -70 70 3.0 3.0 +2.5 +2.5 4.25 1.75 3.0 +50 -120 120 V V mA mA V V V mV mA mA http://onsemi.com 8 AMIS-42770 www..com Table 6. DC AND TIMING CHARACTERISTICS (VCC = 4.75 to 5.25 V; Tjunc = -40 to +150C; RLT = 60 W unless specified otherwise.) Symbol Parameter Conditions Min. Typ. Max. Unit BUS LINES (pins CANH1/2 and CANL1/2) Vi(dif)(th) Differential receiver threshold voltage Differential receiver threshold voltage for high common- mode Differential receiver input voltage hysteresis Common-mode input resistance at pin CANH1/2 Common-mode input resistance at pin CANL1/2 Matching between pin CANH1/2 and pin CANL1/2 common- mode input resistance Differential input resistance Input capacitance at pin CANH1/2 Input capacitance at pin CANL1/2 Differential input capacitance Input leakage current at pin CANH1/2 Input leakage current at pin CANL1/2 Common-mode peak during transition from dom rec or rec dom Difference in common-mode between dominant and recessive state VTx0 = VCC; not tested VTx0 = VCC; not tested VTx0 = VCC; not tested VCC < PORL_VCC; -5.25 V < VCANHx < 5.25 V VCC < PORL_VCC; -5.25 V < VCANLx < 5.25 V See Figure 11 -350 -350 -1000 VCANHx = VCANLx -5 V < VCANLx < +12 V; -5 V < VCANHx < +12 V; see Figure 7 -35 V < VCANLx < +35 V; -35 V < VCANHx < +35 V; see Figure 7 -35 V < VCANL < +35 V; -35 V < VCANH < +35 V; see Figure 7 0.5 0.7 0.9 V Vihcm(dif) (th) 0.3 0.7 1.05 V Vi(dif) (hys) 50 70 100 mV Ri(cm)(CANHx) Ri(cm) (CANLx) Ri(cm)(m) 15 15 -3 26 26 0 37 37 +3 KW KW % Ri(dif) Ci(CANHx) Ci(CANLx) Ci(dif) ILI(CANHx) ILI(CANLx) VCM-peak 25 50 7.5 7.5 3.75 170 170 75 20 20 10 350 350 1000 KW pF pF pF mA mA mV VCM-step See Figure 11 -250 250 mV THERMAL SHUTDOWN Tj(sd) td(Tx-BUSon) td(Tx-BUSoff) td(BUSon-RX) td(BUSoff-RX) td(ENxB) td(Tx-Rx) Shutdown junction temperature 150 C TIMING CHARACTERISTICS (see Figures 8 and 9) Delay Tx0/Text to bus active Delay Tx0/Text to bus inactive Delay bus active to Rx0/Rint Delay bus inactive to Rx0/Rint Delay from EN1B to bus active/inactive Delay from Tx0 to Rx0/Rint and from Text to Rx0 (direct logical path) Time out counter interval Delay for feedback suppression release 15 pF on the digital output 4 40 30 25 65 85 60 55 100 100 10 120 115 115 145 200 35 ns ns ns ns ns ns tdom td(FBS) 15 5+ td(BUSon-RX) 25 45 300 ms ns http://onsemi.com 9 AMIS-42770 www..com Measurement Set-ups and Definitions Schematics are given for single CAN transceiver. +5V 100 nF VCC 12 Text Rint Tx0 4 Rx0 7 10 2 18 17 16 15 6 5 EN2 CANL2 3 9 14 AMIS-42770 19 CANL1 CANH2 1 nF Vref 8 13 CANH1 1 nF Transient Generator GND EN1 Figure 6. Test Circuit for Automotive Transients VRxD High Low Hysteresis 0,5 0,9 Vi(dif)(hys) Figure 7. Hysteresis of the Receiver +5 V 100 nF VCC 12 Text Rint Tx0 4 Rx0 7 10 EN1 2 17 16 15 EN2 6 18 5 CANL2 3 9 14 AMIS-42770 19 CANL1 CANH2 RLT 60 W CLT 100 pF Vref 8 13 CANH1 RLT 60 W CLT 100 pF GND Figure 8. Test Circuit for Timing Characteristics http://onsemi.com 10 AMIS-42770 www..com Tx0 Text 0,7 VCC 0,3 VCC VCANHx-BUS VCANHx VDIFF = VCANHx - VCANLx VCANLx 5V dominant 0V Rx0 Rint 0,9 V 0,5 V 0,7 VCC 0,9 V tPD(H) 0,5 V recessive 0,7 VCC 0,3 VCC td(Tx-Rx) td(Tx-BUSon) td(Tx-Rx) td(Tx-BUSoff) td(BUSon-Rx) 0,3 VCC td(BUSoff-Rx) Figure 9. Timing Diagram for AC Characteristics +5 V 100 nF VCC 12 Text Rint Tx0 Gen 4 Rx0 7 10 EN1 2 17 16 15 EN2 6 18 5 CANL2 47 nF 3 9 14 AMIS-42770 19 CANL1 CANH2 30 W 6.2 kW 30 W Spectrum Anayzer Vref 8 13 CANH1 6.2 kW 10 nF Active Probe GND Figure 10. Basic Test Set-up for Electromagnetic Measurement http://onsemi.com 11 AMIS-42770 www..com CANHx CANLx recessive VCM-peak VCM = 0.5* (VCANHx + VCANLx) VCM-peak VCM-peak Figure 11. Common-mode Voltage Peaks (see Measurement Set-up Figure 10) Company or Product Inquiries For more information about ON Semiconductor's products or services visit our Web site at http://www.onsemi.com. http://onsemi.com 12 AMIS-42770 www..com PACKAGE DIMENSIONS SOIC 20 W CASE 751AQ-01 ISSUE O ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 13 AMIS-42770/D |
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